1. Field of the Invention
The present invention is related to high-speed communications of data in a communication system and, in particular, to high data rate transmission of data between components in a communication system.
2. Discussion of Related Art
Many conventional systems for transmitting data between components within a cabinet or between cabinets of components utilize copper or optical backplanes for transmission of digital data. For example, high data rate transceiver systems are utilized in many backplane environments, including optical switching devices, router systems, switches, chip-to-chip communications and storage area networking switches. Other environments that utilize high speed communication between components include inter-cabinet communications and chip-to-chip chip communications. Typical separations of components in such systems is between about 0.1 and about 10 meters.
Existing techniques utilized in such environments typically use non-return to zero (NRZ) modulation to send and receive information over high-speed backplanes or for high data rate chip-to-chip interconnects. Typically, the transceiver for sending high-speed data over a backplane is called a serializer/deserializer, or SERDES, device.
FIG. 1A shows a block diagram of a backplane environment 100. Components 101-1 through 101-Q are coupled to transmit and receive data through input/output (I/O) ports 102-1 through 102-Q, respectively, to backplane 110. Conventionally, components 101-1 through 101-Q are SERDES devices.
FIG. 1B shows a block diagram of a conventional transmitter portion of one of SERDES devices 101-1 through 101-Q on I/O ports 102-1 through 102-Q, respectively. Parallel data is received in a bit encoder 105. Bit encoder 105 encodes the parallel data, for example by adding redundancy in the input data, to ensure a minimum rate of data transitions in the output data stream. Typical encoding schemes include rate 8/10 (8 bit input to 10 bit output) encoding. The parallel data is serialized in parallel to serial converter 106. Output driver 107 then receives the serialized data from parallel to serial converter 106 and outputs, usually, a differential voltage signal for transmission over backplane 110. In addition, there is typically a phase locked loop (PLL) 114 that provides the necessary clock signals for encoder 105 and parallel-to-serial converter 106. The input signal to PLL 114 is a reference clock signal from a system PLL 103.
FIG. 1C shows a conventional receiver 108 of one of SERDES devices 101-1 through 101-Q on I/O ports 102-1 through 102-Q, respectively, of FIG. 1A. Input driver 109 receives differential voltage signal from backplane 110 and outputs the analog data signal to clock and data recovery circuit 113. Data recovery 113 can, in some systems, perform equalization, recover the timing and output a serial bit stream of data to serial-to-parallel converter 111. The serial data is input to bit decoder 112 which converts the parallel data to parallel decoded data. Clock and data recovery circuit 113 also outputs the necessary clock signals to serial-to-parallel converter 111 and bit decoder 112.
A conventional SERDES system 100 can enable serial data communication at data rates as high as 2.5 Gbps to 3.125 Gbps over a pair of FR4 copper traces in a copper backplane communication system. One of the biggest problems with existing SERDES systems 100 is that they are very bandwidth inefficient, i.e., they require 3.125 GHz of bandwidth to transmit and receive 2.5 Gbps of data over a single pair of copper wires. Therefore, it is very difficult to increase the data rates across backplane bus 110. Additionally, SERDES system 100 requires the implementation of a high clock rate (3.125 GHz for 2.5 Gbps data rates) phase locked loop (PLL) 114 implemented to transmit data and recover high clock rates in data recovery 113. The timing window within which receiver 108 needs to determine whether the received symbol in data recovery 115 is a 1 or a 0 is about 320 ps for the higher data rate systems. This timing window creates extremely stringent requirements on the design of data recovery 115 and PLL 114, as they must have very low peak-to-peak jitter.
Conventional SERDES system 100 also suffers from other problems, including eye closure due to intersymbol interference (ISI) from the dispersion introduced by backplane 110. The ISI is a direct result of the fact that the copper traces of backplane 110 attenuate higher frequency components in the transmitted signals more than the lower frequency components in the transmitted signal. Therefore, the higher the data rate the more ISI suffered by the transmitted data. In addition, electrical connectors and electrical connections (e.g., vias and other components) used in SERDES device 100 cause reflections, which also cause ISI.
To overcome these problems, equalization must be performed on the received signal in data recovery 113. However, in existing very high data-rate communication systems, equalization is very difficult to perform, if not impossible due to the high baud rate. A more commonly utilized technique for combating ISI is known as “pre-emphasis”, or pre-equalization, performed in bit encoder 105 and output driver 107 during transmission. In some conventional systems, the amplitude of the low-frequencies in the transmitted signal is attenuated to compensate for the higher attenuation of the high frequency component by the transmission medium of bus 110. While this makes the receiver more robust to ISI, pre-emphasis reduces the overall noise tolerance of transmission over backplane 110 of backplane communication system 100 due to the loss of signal-to-noise ratio (SNR). At higher data rates, conventional systems quickly become intractable due to the increased demands.
Therefore, there is a need for a more robust system for transmitting data between components on a backplane or data bus at very high speeds.